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d a t a sh eet product speci?cation file under integrated circuits, ic06 december 1990 integrated circuits 74hc/hct193 presettable synchronous 4-bit binary up/down counter for a complete data sheet, please also download: the ic06 74hc/hct/hcu/hcmos logic family specifications the ic06 74hc/hct/hcu/hcmos logic package information the ic06 74hc/hct/hcu/hcmos logic package outlines
december 1990 2 philips semiconductors product speci?cation presettable synchronous 4-bit binary up/down counter 74hc/hct193 features synchronous reversible 4-bit binary counting asynchronous parallel load asynchronous reset expandable without external logic output capability: standard i cc category: msi general description the 74hc/hct193 are high-speed si-gate cmos devices and are pin compatible with low power schottky ttl (lsttl). they are specified in compliance with jedec standard no. 7a. the 74hc/hct193 are 4-bit synchronous binary up/down counters. separate up/down clocks, cp u and cp d respectively, simplify operation. the outputs change state synchronously with the low-to-high transition of either clock input. if the cp u clock is pulsed while cp d is held high, the device will count up. if the cp d clock is pulsed while cp u is held high, the device will count down. only one clock input can be held high at any time, or erroneous operation will result. the device can be cleared at any time by the asynchronous master reset input (mr); it may also be loaded in parallel by activating the asynchronous parallel load input ( pl). the 193 contains four master-slave jk flip-flops with the necessary steering logic to provide the asynchronous reset, load, and synchronous count up and count down functions. each flip-flop contains jk feedback from slave to master, such that a low-to-high transition on the cp d input will decrease the count by one, while a similar transition on the cp u input will advance the count by one. one clock should be held high while counting with the other, otherwise the circuit will either count by twos or not at all, depending on the state of the first flip-flop, which cannot toggle as long as either clock input is low. applications requiring reversible operation must make the reversing decision while the activating clock is high to avoid erroneous counts. the terminal count up ( tc u ) and terminal count down ( tc d ) outputs are normally high. when the circuit has reached the maximum count state of 15, the next high-to-low transition of cp u will cause tc u to go low. tc u will stay low until cp u goes high again, duplicating the count up clock. likewise, the tc d output will go low when the circuit is in the zero state and the cp d goes low. the terminal count outputs can be used as the clock input signals to the next higher order circuit in a multistage counter, since they duplicate the clock waveforms. multistage counters will not be fully synchronous, since there is a slight delay time difference added for each stage that is added. the counter may be preset by the asynchronous parallel load capability of the circuit. information present on the parallel data inputs (d 0 to d 3 ) is loaded into the counter and appears on the outputs (q 0 to q 3 ) regardless of the conditions of the clock inputs when the parallel load ( pl) input is low. a high level on the master reset (mr) input will disable the parallel load gates, override both clock inputs and set all outputs (q 0 to q 3 ) low. if one of the clock inputs is low during and after a reset or load operation, the next low-to-high transition of that clock will be interpreted as a legitimate signal and will be counted.
december 1990 3 philips semiconductors product speci?cation presettable synchronous 4-bit binary up/down counter 74hc/hct193 quick reference data gnd = 0 v; t amb = 25 c; t r = t f = 6 ns notes 1. c pd is used to determine the dynamic power dissipation (p d in m w): p d = c pd v cc 2 f i +? (c l v cc 2 f o ) where: f i = input frequency in mhz f o = output frequency in mhz ? (c l v cc 2 f o ) = sum of outputs c l = output load capacitance in pf v cc = supply voltage in v 2. for hc the condition is v i = gnd to v cc for hct the condition is v i = gnd to v cc - 1.5 v ordering information see 74hc/hct/hcu/hcmos logic package information . symbol parameter conditions typical unit hc hct t phl / t plh propagation delay cp d , cp u to q n c l = 15 pf; v cc = 5 v 20 20 ns f max maximum clock frequency 45 47 mhz c i input capacitance 3.5 3.5 pf c pd power dissipation capacitance per package notes 1 and 2 24 26 pf
december 1990 4 philips semiconductors product speci?cation presettable synchronous 4-bit binary up/down counter 74hc/hct193 pin description note 1. low-to-high, edge triggered pin no. symbol name and function 3, 2, 6, 7 q 0 to q 3 ?ip-?op outputs 4cp d count down clock input (1) 5cp u count up clock input (1) 8 gnd ground (0 v) 11 pl asynchronous parallel load input (active low) 12 tc u terminal count up (carry) output (active low) 13 tc d terminal count down (borrow) output (active low) 14 mr asynchronous master reset input (active high) 15, 1, 10, 9 d 0 to d 3 data inputs 16 v cc positive supply voltage fig.1 pin configuration. fig.2 logic symbol. fig.3 iec logic symbol.
december 1990 5 philips semiconductors product speci?cation presettable synchronous 4-bit binary up/down counter 74hc/hct193 function table notes 1. h = high voltage level l = low voltage level x = dont care - = low-to-high clock transition 2. tc u =cp u at terminal count up (hhhh) 3. tc d =cp d at terminal count down (llll) operating mode inputs outputs mr pl cp u cp d d 0 d 1 d 2 d 3 q 0 q 1 q 2 q 3 tc u tc d reset (clear) h h x x x x l h x x x x x x x x l l l l l l l l h h l h parallel load l l l l l l l l x x l h l h x x l l h h l l h h l l h h l l h h l l h h l l h h l l h h l l h h h h l h l h h h count up l h - h x x x x count up h (2) h count down l h h - x x x x count down h h (3) fig.4 functional diagram.
december 1990 6 philips semiconductors product speci?cation presettable synchronous 4-bit binary up/down counter 74hc/hct193 fig.5 typical clear, load and count sequence. (1) clear overrides load, data and count inputs. (2) when counting up the count down clock input (cp d ) must be high, when counting down the count up clock input (cp u ) must be high. sequence clear (reset outputs to zero); load (preset) to binary thirteen; count up to fourteen, fifteen, terminal count up, zero, one and two; count down to one, zero, terminal count down, fifteen, fig.6 logic diagram.
december 1990 7 philips semiconductors product speci?cation presettable synchronous 4-bit binary up/down counter 74hc/hct193 dc characteristics for 74hc for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: standard i cc category: msi ac characteristics for 74hc gnd = 0 v; t r = t f = 6 ns; c l = 50 pf symbol parameter t amb ( c) unit test conditions 74hc v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. t phl / t plh propagation delay cp u ,cp d to q n 63 23 18 215 43 37 270 54 46 325 65 55 ns 2.0 4.5 6.0 fig.7 t phl / t plh propagation delay cp u to tc u 39 14 11 125 25 21 155 31 26 190 38 32 ns 2.0 4.5 6.0 fig.8 t phl / t plh propagation delay cp d to tc d 39 14 11 125 25 21 155 31 26 190 38 32 ns 2.0 4.5 6.0 fig.8 t phl / t plh propagation delay pl to q n 69 25 20 220 44 37 275 55 47 330 66 56 ns 2.0 4.5 6.0 fig.9 t phl propagation delay mr to q n 58 21 17 200 40 34 250 50 43 300 60 51 ns 2.0 4.5 6.0 fig.10 t phl / t plh propagation delay d n to q n 69 25 20 210 42 36 265 53 45 315 63 54 ns 2.0 4.5 6.0 fig.9 t phl / t plh propagation delay pl to tc u , pl to tc d 80 29 23 290 58 49 365 73 62 435 87 74 ns 2.0 4.5 6.0 fig.12 t phl / t plh propagation delay mr to tc u ,mrto tc d 74 27 22 285 57 48 355 71 60 430 86 73 ns 2.0 4.5 6.0 fig.12 t phl / t plh propagation delay d n to tc u ,d n to tc d 80 29 23 290 58 49 365 73 62 435 87 74 ns 2.0 4.5 6.0 fig.12 t thl / t tlh output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 fig.10 t w up, down clock pulse width high or low 100 20 17 22 8 6 125 25 21 150 30 26 ns 2.0 4.5 6.0 fig.7
december 1990 8 philips semiconductors product speci?cation presettable synchronous 4-bit binary up/down counter 74hc/hct193 t w master reset pulse width high 100 20 17 25 9 7 125 25 21 150 30 26 ns 2.0 4.5 6.0 fig.10 t w parallel load pulse width low 100 20 17 19 7 6 125 25 21 150 30 26 ns 2.0 4.5 6.0 fig.9 t rem removal time pl to cp u ,cp d 50 10 9 8 3 2 65 13 11 75 15 13 ns 2.0 4.5 6.0 fig.9 t rem removal time mr to cp u ,cp d 50 10 9 0 0 0 65 13 11 75 15 13 ns 2.0 4.5 6.0 fig.10 t su set-up time d n to pl 80 16 14 22 8 6 100 20 17 120 24 20 ns 2.0 4.5 6.0 fig.11 note: cp u = cp d = high t h hold time d n to pl 0 0 0 - 14 - 5 - 4 0 0 0 0 0 0 ns 2.0 4.5 6.0 fig.11 t h hold time cp u to cp d , cp d to cp u 80 16 8 22 8 6 100 20 17 120 24 20 ns 2.0 4.5 6.0 fig.13 f max maximum up, down clock pulse frequency 4.0 20 24 13.5 41 49 3.2 16 19 2.6 13 15 mhz 2.0 4.5 6.0 fig.7 symbol parameter t amb ( c) unit test conditions 74hc v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max.
december 1990 9 philips semiconductors product speci?cation presettable synchronous 4-bit binary up/down counter 74hc/hct193 dc characteristics for 74hct for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: standard i cc category: msi note to hct types the value of additional quiescent supply current ( d i cc ) for a unit load of 1 is given in the family specifications. to determine d i cc per input, multiply this value by the unit load coefficient shown in the table below. input unit load coefficient d n cp u ,cp d pl mr 0.35 1.40 0.65 1.05
december 1990 10 philips semiconductors product speci?cation presettable synchronous 4-bit binary up/down counter 74hc/hct193 ac characteristics for 74hct gnd = 0 v; t r = t f = 6 ns; c l = 50 pf symbol parameter t amb ( c) unit test conditions 74hct v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. t phl / t plh propagation delay cp u ,cp d to q n 23 43 54 65 ns 4.5 fig.7 t phl / t plh propagation delay cp u to tc u 15 27 34 41 ns 4.5 fig.8 t phl / t plh propagation delay cp d to tc d 15 27 34 41 ns 4.5 fig.8 t phl / t plh propagation delay pl to q n 26 46 58 69 ns 4.5 fig.9 t phl propagation delay mr to q n 22 40 50 60 ns 4.5 fig.10 t phl / t plh propagation delay d n to q n 27 46 58 69 ns 4.5 fig.9 t phl / t plh propagation delay pl to tc u , pl to tc d 31 55 69 83 ns 4.5 fig.12 t phl / t plh propagation delay mr to tc u , mr to tc d 29 55 69 83 ns 4.5 fig.12 t phl / t plh propagation delay d n to tc u ,d n to tc d 32 58 73 87 ns 4.5 fig.12 t thl / t tlh output transition time 7 15 19 22 ns 4.5 fig.10 t w up, down clock pulse width high or low 25 11 31 38 ns 4.5 fig.7 t w master reset pulse width high 20 7 25 30 ns 4.5 fig.10 t w parallel load pulse width low 20 8 25 30 ns 4.5 fig.9 t rem removal time pl to cp u ,cp d 10 2 13 15 ns 4.5 fig.9 t rem removal time mr to cp u ,cp d 10 0 13 15 ns 4.5 fig.10 t su set-up time d n to pl 16 8 20 24 ns 4.5 fig.11 note: cp u =cp d = high t h hold time d n to pl 0 - 6 0 0 ns 4.5 fig.11 t h hold time cp u to cp d ,cp d to cp u 16 7 20 24 ns 4.5 fig.13 f max maximum up, down clock pulse frequency 20 43 16 13 mhz 4.5 fig.7
december 1990 11 philips semiconductors product speci?cation presettable synchronous 4-bit binary up/down counter 74hc/hct193 ac waveforms fig.7 waveforms showing the clock (cp u , cp d ) to output (q n ) propagation delays, the clock pulse width, and the maximum clock pulse frequency. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3v; v i = gnd to 3 v. fig.8 waveforms showing the clock (cp u ,cp d ) to terminal count output ( tc u , tc d ) propagation delays. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3v; v i = gnd to 3 v. fig.9 waveforms showing the parallel load input ( pl) and data (d n ) to q n output propagation delays and pl removal time to clock input (cp u ,cp d ). (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3v; v i = gnd to 3 v.
december 1990 12 philips semiconductors product speci?cation presettable synchronous 4-bit binary up/down counter 74hc/hct193 fig.10 waveforms showing the master reset input (mr) pulse width, mr to q n propagation delays, mr to cp u , cp d removal time and output transition times. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3v; v i = gnd to 3 v. fig.11 waveforms showing the data input (d n ) to parallel load input ( pl) set-up and hold times. the shaded areas indicate when the input is permitted to change for predictable output performance. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3v; v i = gnd to 3 v. fig.12 waveforms showing the data input (d n ), parallel load input ( pl) and the master reset input (mr) to the terminal count outputs ( tc u , tc d ) propagation delays. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3v; v i = gnd to 3 v. fig.13 waveforms showing the cp u to cp d or cp d to cp u hold times. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3v; v i = gnd to 3 v.
december 1990 13 philips semiconductors product speci?cation presettable synchronous 4-bit binary up/down counter 74hc/hct193 application information package outlines see 74hc/hct/hcu/hcmos logic package outlines . fig.14 cascaded up/down counter with parallel load.

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